library ieee ;
use ieee.std_logic_1164.all;
use work.all;

-- Definicion
entity cmp_dff is
    port( data_in:  in std_logic;
          clock:    in std_logic;
          data_out: inout std_logic );
end cmp_dff;

-- Arquitectura
architecture behv of cmp_dff is

    component cmp_dlatch
        port(data_in:    in std_logic;
             e:          in std_logic;
             data_out:   inout std_logic );
    end component;

    component cmp_not
        port( D_in:  in std_logic;
              D_out: out std_logic );
    end component;

    signal Q0: std_logic;
    signal notClock: std_logic;

begin
    dlatch_0: cmp_dlatch port map (data_in, notClock, Q0);
    not_0:    cmp_not port map (clock, notClock);
    dlatch_1: cmp_dlatch port map (Q0, clock, data_out);
end behv;

